With the wide use and rapid development of random access memories ("RAM"), especially dynamic random access memories ("DRAM"), the storage capacity of memory devices doubles approximately every two years. In addition, different types of memory devices, such as DRAMS with different storage capacities, are now available in the market. They include DRAMS of sizes 256 k.times.1, 1 M.times.1, 4 M.times.1, 16 M.times.1, 256 k.times.4, 1 M.times.4, 4 M.times.4, and soon will include wider DRAMS with storage capacity of 256 k.times.16 and 1 M.times.16. However, the questions of how to provide a main memory structure which can efficiently support different processor and bus systems, and allow the use of different types of memory devices, have not yet been solved by the prior art. Further, if such a main memory is provided, the next issue is providing a memory controller which can efficiently control the access to such memory in accordance with different processor system requirements.
In order to satisfy different processor system requirements, a variety of different system buses have been introduced having different bandwidths to support different processors. These buses may also have different bus clock frequencies.
One bus available on the market is a bus called MBus, developed by Sun Microsystems Inc., which is compatible with complementary metal-oxide semiconductor (CMOS) technology. The MBus is normally classified into two levels. Level 1 supports a single processor system. An example of a uniprocessor system is generally shown in FIG. 1A, in which bus 2 is coupled between processor 3 and memory controller 4, the latter connected to memory 5. Another example of a uniprocessor system is shown in FIG. 1B, wherein the processor 6 is coupled to a cache 7 which is further coupled to a system bus 8. Level 2 supports multi-processor systems. An example of a multi-processor system 10 is shown in FIG. 1C. A plurality of processors 11-12 (only two are shown) share common main memory 17 through bus 15 and memory controller 16, with each processor 11 or 12 associated with at least one local cache 13 or 14. An example of the level 2 MBus is the SPARC.RTM. MBus Level 2 which can support normal read and write transactions plus a number of additional transactions including coherent invalidate transactions, coherent read transactions, coherent write and invalidate transactions, and coherent read and invalidate transactions. Each of these latter transactions requires that a local cache be associated with each processor. Although the SPARC MBus is defined currently with a 64 bit system bus operating at 40 MHz, system buses may have different bus sizes, such as 32-, 64- and 128-bit data widths, and different clock frequencies, such as 25 MHz, 33 MHz, 40 MHz, or 50 MHz.
Conventional memory systems are not flexible enough to support a variety of buses which each have different bus sizes and clock rates. In particular, conventional memory systems do not efficiently support bus systems which are coupled to a number of processors, each of which is associated with at least one local cache, and which share a common main memory.
For example, in some processor systems, cache controllers in copyback environments may not have internal buffering allowing them to purge the cache line internally, and then request a read of the main memory (a DRAM), followed by a write of the old cache line back to the main memory. They frequently are required to perform the write to main memory first, followed by the read. This wastes processor cycle time waiting for the missed cache line to be filled. Conventional memory systems have no mechanism to support a cache purge operation. In addition, during a coherent read transaction, conventional memory controllers can only monitor the transaction without being able to convert the inhibited read operation to write operation, thereby implementing a reflective memory.
Some conventional memory controllers are provided with a data buffering device, such as a FIFO, to buffer normal write or read data. However, the configuration of such controllers are generally not suitable for support of the above mentioned cache purge or reflective read operations. Further, such controllers cannot efficiently perform a data transaction between main memory and the system bus when the data buffering device is occupied by a previous transaction. In addition, short byte and long burst transactions normally cannot be performed in an efficient and reliable manner.
Finally, conventional memory systems are not flexible enough to enhance the timing resolution of the memory in accordance with different system bus clock frequencies.
Examples of these conventional memory systems are disclosed in the following references: U.S. Pat. No. 4,954,951 issued on Sep. 4, 1990; a product specification of Advanced Micro Devices titled "4M Configurable Dynamic Memory Controller/Driver", product No. AM29C668, published in March, 1990; a product specification of SAMSUNG titled "Dynamic RAM Controllers", product No. KS84C31/32, published in November, 1989; a product specification of Signetics titled "Intelligent DRAM Controller", product No. FAST 74F1763, published on May 12, 1989; a product specification of Signetics titled "DRAM and Interrupt Vector Controller" product No FAST 74F1761, published on May 5, 1989; and an article by Brian Case titled "MBus Provides Processor--Independent Bus", published in Microprocessor Report on Aug. 7, 1991, pp. 8-12.